FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
Mehdi Alipour1,a, Rakesh Kumar2, Stefanos Kaxiras1,b and David Black-Schaffer1,c
1Department of Information Technology, Uppsala University, Sweden
amehdi.alipour@it.uu.se
bstefanos.kaxiras@it.uu.se
cdavid.schaffer@it.uu.se
2Department of Computer Science , Norwegian University of Science and Technology, Norway
rakesh.kumar@ntnu.no
ABSTRACT
The number of instructions a processor’s instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order.
This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, inorder FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor’s overall issue width and depth.
Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance.
