Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming
Mustafa M. Shihaba, Jingxiang Tianb, Gaurav Rajavendra Reddyc, Bo Hud, William Swartz Jr.e, Benjamin Carrion Schaeferf, Carl Secheng and Yiorgos Makrish
The University of Texas at Dallas, Richardson, USA
amustafa.shihab@utdallas.edu
bjingxiang.tian@utdallas.edu
cgaurav.reddy@utdallas.edu
dbo.hu4@utdallas.edu
ebill-swartz@utdallas.edu
fschaferb@utdallas.edu
gcarl.sechen@utdallas.edu
hyiorgos.makris@utdallas.edu
ABSTRACT
Widespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, concerted interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction and usage of ICs has surfaced. To this end, in this paper we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication TRAnsistorlevel Programming (TRAP). We introduce a transistor-level programmable fabric and we discuss its unique advantages towards design obfuscation, as well as a customized CAD framework for seamlessly integrating this fabric in an ASIC design flow. We theoretically analyze the complexity of attacking TRAPobfuscated designs through both brute-force and intelligent SATbased attacks and we present a silicon implementation of a platform for experimenting with TRAP. Effectiveness of the proposed method is evaluated through selective obfuscation of various modules of a modern microprocessor design. Results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks, while incurring an order of magnitude less area, power and delay overhead.
