Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT
Hela Belhadj Amor and Carolynn Berniera
IC Design, Architectures and Embedded Software Department Univ. Grenoble Alpes, CEA, Grenoble, France
acarolynn.bernier@cea.fr
ABSTRACT
This work demonstrates an ultra-low power, software-defined wireless transceiver designed for IoT applications using an open-source 32-bit RISC-V core. The key driver behind this success is an optimized hardware/software partitioning of the receiver’s digital signal processing operators. We benchmarked our architecture on an algorithm for the detection of FSK-modulated frames using a RISC-V compatible core and ARM Cortex-M series processors. We use only standard compilation tools and no assembly-level optimizations. Our results show that Bluetooth LE frames can be detected with an estimated peak core power consumption of 1.6 mW on a 28 nm FDSOI technology, and falling to less than 0.6 mW (on average) during symbol demodulation. This is achieved at nominal voltage. Compared to state of the art, our work offers a power efficient alternative to the design of dedicated baseband processors for ultra-low power software-defined radios with a low software complexity.
Keywords: IoT, LPWA, software-defined radio, RISC-V.
