Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation
Tingyou Lin1,a, Chauchin Su1,b, Chung-Chih Hung1,c, Karuna Nidhi2,d, Chily Tu2,e and Shao-Chang Huang2,f
1National Chiao Tung University, Hsinchu, Taiwan
aliam0.cm98g@g2.nctu.edu.tw
bccsu@mail.nctu.edu.tw
ccchung@mail.nctu.edu.tw
2Vanguard International Semiconductor Corporation, Hsinchu, Taiwan
dknidhi@vis.com.tw
ecltu@vis.com.tw
fschuangq@vis.com.tw
ABSTRACT
This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate a 10kμm power MOSFET has Ron increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has Ron increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.
Keywords: Accelerated aging, Accelerated testing, Power MOSFET.
