An Evolutionary Approach to Hardware Encryption and Trojan-Horse Mitigation
Andrea Marcellia, Marco Restifob, Ernesto Sanchezc and Giovanni Squillerod
Politecnico di Torino, Corso Duca degli Abruzzi, Torino 10129, Italy.
aandrea.marcelli@polito.it
bmarco.restifo@polito.it
cernesto.sanchez@polito.it
dgiovanni.squillero@polito.it
ABSTRACT
New threats, grouped under the name of hardware attacks, became a serious concern in recent years. In a global market, untrusted parties in the supply chain may jeopardize the production of integrated circuits with intellectual-property piracy, illegal overproduction and hardware Trojan-horses (HT) injection. While one way to protect from overproduction is to encrypt the design by inserting logic gates that prevents the circuit from generating the correct outputs unless the right key is used, reducing the number of poorly-controllable signals is known to minimize the chances for an attacker to successfully hide the trigger for some malicious payload. Several approaches successfully tackled independently these two issues. This paper proposes a novel technique based on a multi-objective evolutionary algorithm able to increase hardware security by explicitly targeting both the minimization of rare signals and the maximization of the efficacy of logic encryption. Experimental results demonstrate the proposed method is effective in creating a secure encryption schema for all the circuits under test and in reducing the number rare signals on six circuits over nine, outperforming the current state of the art.
