Pushing the Limits of Voltage Over-Scaling for Error-Resilient Applications
Rengarajan Ragavan1,a, Benjamin Barrois1,b, Cedric Killian1,c and Olivier Sentieys2
1Univ. Rennes 1 - IRISA/INRIA.
arengarajan.ragavan@irisa.fr
bbenjamin.barrois@irisa.fr
ccedric.killian@irisa.fr
2INRIA/IRISA.
olivier.sentieys@inria.fr
ABSTRACT
Voltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are proposing voltage over-scaling based approximate operators for applications that can tolerate errors. We characterize the basic arithmetic operators using different operating triads (combination of supply voltage, body-biasing scheme and clock frequency) to generate models for approximate operators. Error-resilient applications can be mapped with the generated approximate operator models to achieve optimum trade-off between energy efficiency and error margin. Based on the dynamic speculation technique, best possible operating triad is chosen at runtime based on the user definable error tolerance margin of the application. In our experiments in 28nm FDSOI, we achieve maximum energy efficiency of 89% for basic operators like 8-bit and 16-bit adders at the cost of 20% Bit Error Rate (ratio of faulty bits over total bits) by operating them in near-threshold regime.
