HARPA: Tackling Physically Induced Performance Variability
Nikolaos Zompakis1, Michail Noltsis1, Lorena Ndreu2, Zacharias Hadjilambrou2, Panagiotis Englezakis2, Panagiota Nikolaou2, Antoni Portero3, Simone Libutti4, Giuseppe Massari4, Federico Sassi5, Alessandro Bacchini5, Chrysostomos Nicopoulos2, Yiannakis Sazeides2, Radim Vavrik3, Martin Golasowski3, Jiri Sevcik3, Vit Vondrak3, Francky Catthoor6, William Fornaciari4 and Dimitrios Soudris1
1MicroLab-ECE-NTUA, Greece
2University of Cyprus, Cyprus
3IT4Innovations, National Supercomputing Center, the Czech Republic
4DEIB - Politecnico di Milano, Italy
5IMEC, Belgium
6Camlin Italy s.r.l., Italy
ABSTRACT
Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an everlasting scaling of devices in silicon. Nevertheless, integration and miniaturization of transistors comes with an important and nonnegligible trade-off: time-zero and time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins are prohibitive for downscaled technology nodes. This paper discusses the FP7-612069-HARPA project of the European Commission which aims to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the ES or HPC domains (worstcase guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance).
