Fast Low Power Rule Checking for Multiple Power Domain Design
Chien-Pang Lu1 and Iris Hui-Ru Jiang2
1MediaTek Inc., Hsinchu 30078, Taiwan.
Knuth.Lu@mediatek.com
2Dept. of Electronics Eng., National Chiao Tung Univ., Hsinchu 30010, Taiwan.
huiru.jiang@gmail.com
ABSTRACT
Power management via multiple power domains can effectively save power by dynamically turning off idle domains. To control domains of a design, introducing low power intent complicates the physical implementation and verification process. During the physical implementation stage, the optimization or manual ECO could be tedious, and error-prone on power/ground signal connections. Therefore, in this paper, we focus on low power rule checking at the physical implementation stage for multiple power domain design. Existing methods adopt an iterative approach, which identifies one error at a time, thus possibly requiring multiple iterations. Different from them, we propose a fast low power rule checking approach to detect all errors at one time. To do so, we separate all paths into innerdomain and cross-domain paths and extract cross-domain net topology before power rule verification. Based on the global topology, we can verify the correctness of connections and detect all errors at the same time. Experimental results show the effectiveness and efficiency of our approach, achieving 3.62X speedups to detect all errors compared with the iterative approach. Moreover, our approach can identify complicated bugs to facilitate subsequent bug fixing.
Keywords: Power management, Multiple power domains, Power rules, IEEE standard 1801.
