Workload Dependent Reliability Timing Analysis Flow
Ajith Sivadasan1,2,a, Armelle Notin1, Vincent Huard1, Etienne Maurin1, Souhir Mhira1, Florian Cacho1 and Lorena Anghel2
1STMicroelectronics - 850 rue Jean Monnet, 38926 Crolles, France.
aajith.sivadasan@st.com
2TIMA, 46, avenue felix Viallet, 38031 Grenoble, France
ABSTRACT
Silicon measurements indicate a change in frequency limiting path rankings as per aging and also as a function of workload. This paper proposes a simulation flow that leads to the identification of workload specific aged critical paths. Gate-level models are a means to estimate aging of the critical paths by taking into consideration the stress experienced by corresponding standard cells for a given digital circuit workload during circuit operational lifetime. We thus estimate the workload based aging margins for a particular design using this simulation flow.
Keywords: Workload, Aging, Critical path, Reliability.
