Clock Data Compensation Aware Clock Tree Synthesis in Digital Circuits with Adaptive Clock Generation
Taesik Naa, Jong Hwan Kob and Saibal Mukhopadhyayc
School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA.
ataesik.na@gatech.edu
bjonghwan.ko@gatech.edu
csaibal@ece.gatech.edu
ABSTRACT
Adaptive clock generation to track critical path delay enables lowering supply voltage with improved timing slack under supply noise. This paper presents how to synthesize clock tree in adaptive clocking to fully exploit the clock data compensation (CDC) effect in digital circuits. The paper first provides analytical proof of ideal CDC effect for ring oscillator based clock generation. Second, the paper analyzes non-ideal CDC effect in a gate dominated critical path and wire dominated clock tree design. The paper shows the delay sensitivity mismatch between clock tree and critical path can degrade CDC effect by analyzing timing slack under power supply noise (PSN). Finally, the paper proposes simple but efficient clock tree synthesis (CTS) technique to maximize timing slack under PSN in digital circuits with adaptive clock generation.
Keywords: Clock data compensation, Clock tree synthesis, Adaptive clock.
