Register Transfer Level Information Flow Tracking for Provably Secure Hardware Design
Armaiti Ardeshiricham, Wei Hu, Joshua Marxen and Ryan Kastner
Dept. of Computer Science and Engineering, University of California, San Diego
ABSTRACT
Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning about security properties related to integrity, confidentiality, and logical side channel. Recently, IFT has been employed for secure hardware design and verification. However, existing hardware IFT techniques either require designers to rewrite their hardware specifications in a new language or do not scale to large designs due to a low level of abstraction. In this work, we propose Register Transfer Level IFT (RTLIFT), which enables verification of security properties in an early design phase, at a higher level of abstraction, and directly on RTL code. The proposed method enables a precise understanding of all logical flows through RTL design and allows various tradeoffs in IFT precision. We show that RTLIFT achieves over 5 38 215; speedup in verification performance as compared to gate level IFT while minimizing the required effort for the designer to verify security properties on RTL designs.
