Droop Mitigating Last Level Cache Architecture for STTRAM

Radha Krishna Aluru1 and Swaroop Ghosh2
1Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA.
2School of Electrical Engineering and Computer Science, Pennsylvania State University, University Park, PA-16801, USA.


Spin-Transfer Torque Random Access Memory (STTRAM) is one of the emerging Non-Volatile Memory (NVM) technologies especially preferred for the Last Level Cache (LLC). The amount of current needed to switch the magnetization is high (\sima100mA per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop, the write operation fails especially, when the farthest bank of the cache is accessed. In this paper, we propose a new cache architecture to mitigate this problem of droop and make the write operation successful. Instead of continuously writing the entire cache line (512-bit) in a single bank, the proposed architecture writes 64-bits in multiple physically separated locations across the cache. The simulation results obtained (both circuit and micro-architectural) comparing our proposed architecture against the conventional are found to be 1.96% (IPC) and 5.21% (energy).

Keywords: Droop, LLC, STTRAM, Bank, Latency, Energy, SPLASH benchmarks.

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