An On-Line Framework for Improving Reliability of Real-Time Systems on "Big-Little" Type MPSoCs
Yue Ma1,a, Thidapat Chantem2, Robert P. Dick3, Shige Wang4 and X. Sharon Hu1,b
1Department of CSE, University of Notre Dame, Notre Dame, IN 46656, USA.
ayma1@nd.edu
bshu@nd.edu
2Department of ECE, Virginia Polytechnic Institute and State University, Arlington, VA.
tchantem@vt.edu
3Department of EECS, University of Michigan, Ann Arbor, MI.
dickrp@umich.edu
4General Motors R 38 D
shige.wang@gm.com
ABSTRACT
Heterogeneous MPSoCs consisting of cores with different performance/power behaviors are widely used in many power-constrained real-time systems. Both soft-error reliability and lifetime reliability are key concerns in such systems. Although existing work have investigated related problems, they either focus on one of the two reliability concerns or propose complicated scheduling algorithms that cannot adequately address run-time workload and environment variations. This paper introduces an on-line heuristic to maximize soft-error reliability while satisfying a lifetime reliability constraint for soft real-time systems executed on MPSoCs composed of high-performance cores and low-power cores. Based on the run-time cores', frequencies and utilizations, the heuristic performs workload migration between the highperformance cores and low-power cores to achieve improved soft-error reliability. Experimental results from both a hardware platform and a simulator show that the proposed algorithm reduces the probability of faults by at least 30% compared to a number of representative existing approaches while satisfying the same lifetime reliability constraints.
Keywords: Soft-error reliability, Lifetime reliability, Heterogeneous MPSoC, Real-time embedded system.
