Robust TSV-based 3D NoC Design to Counteract Electromigration and Crosstalk Noise

Sourav Das1,a, Janardhan Rao Doppa1,b, Partha Pratim Pande1,c and Krishnendu Chakrabarty2
1School of EECS, Washington State University, Pullman, WA, USA.
2Department of ECE, Duke University, Durham, NC, USA.


A 3D network-on-chip (3D NoC) is an enabler for the design of high-performance and energy-efficient manycore chips. Most popular 3D NoCs utilize the Through-Silicon-Via (TSV)-based vertical links (VLs) as the communication pillars between the planar dies. However, the TSVs in a 3D NoC may fail due to both workload-induced stress and crosstalk capacitance. This failure negatively affects the overall achievable performance of the 3D NoC. In this work, we analyze the joint effects of workload-induced stress and crosstalk on the TSV mean-time-to-failure (MTTF) and hence the 3D NoC lifetime. We demonstrate that if we only consider the effects of electromigration on the TSVs due to workload-induced stress then the estimated MTTF and the subsequently lifetime of 3D NoC are too optimistic. Due to the combined effects of workload and crosstalk noise, the lifetime of 3D NoC reduces significantly. Subsequently, we demonstrate that a spare TSV allocation methodology considering the joint effects of workload and crosstalk noise enhances the lifetime of the 3D NoC by a factor of 4.6 compared to when only the workload is considered for a given spare budget of 5%.

Keywords: Crosstalk, Electromigration, TSVs, MTTF, 3D NoC, Manycore chip, Lifetime, Reliability.

Full Text (PDF)