A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration
Jingxiang Tiana, Gaurav Rajavendra Reddyb, Jiajia Wangc, William Swartz Jr.d, Yiorgos Makrise and Carl Sechenf
Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX.
ajxt122130@utdallas.edu
bgxr141930@utdallas.edu
cjxw143630@utdallas.edu
dwps100020@utdallas.edu
egxm112130@utdallas.edu
fcms057000@utdallas.edu
ABSTRACT
We introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. Termed Field Programmable Transistor Array (FPTA), this novel reconfigurable architecture enables several highly-desirable features including (i) simultaneous storage of three configurations along with the ability to dynamically switch between them in a fraction of a single cycle, while retaining the fabric's computational state, (ii) rapid or full modification of a stored configuration in a time proportional to the number of modified configuration bits through the use of hierarchically arranged, high throughput, asynchronously pipelined memory buffers, and (iii) support for libraries containing cells of the same height and variable width, just as in a typical standard cell circuit, thereby simplifying transition from a prototype to a custom IC design. Besides presenting the design details of this fabric in a 130nm technology and demonstrating the aforementioned capabilities, we also briefly discuss the development of a complete CAD flow for programing this fabric and we use numerous benchmark circuits to contrast its area efficiency against a typical FPGA implemented in the same technology node.
