Verification of Networked Labs-on-Chip Architectures

Andreas Grimmer1,a, Werner Haselmayr2,c, Andreas Springer2,d and Robert Wille1,3,b
1Institute for Integrated Circuits, Johannes Kepler University Linz, Austria.
2Institute for Communications Engineering and RF-Systems, Johannes Kepler University Linz, Austria.
3Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany


Labs-on-Chips (LoCs) revolutionize conventional biochemical processes and may even replace laboratories by integrating and minimizing their functionalities on a single chip. In a promising and emerging realization of LoCs, small volumes of reagents, so-called droplets, transport the biological sample and flow in closed channels of sub-millimeter diameters. This realization is called Networked Labs-on-Chips (NLoCs). The architecture of an NLoC defines different paths through which the droplets can flow. These paths are realized by splitting channels into multiple successor channels - so-called bifurcations. However, whether the architecture indeed allows to route droplets along the desired paths and, hence, correctly executes the intended experiment is not guaranteed. In this work, we present the first automatic solution for verifying whether an NLoC architecture allows to correctly route the droplets. Our evaluations demonstrate the applicability and importance of the proposed solution on a set of NLoC architectures.

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