Timing-Aware Wire Width Optimization for SADP Process

Youngsoo Song, Sangmin Kim and Youngsoo Shin
School of Electrical Engineering, KAIST, Daejeon 34141, Korea


Wire width optimization for SADP process is addressed, which involves a decision of how cut- and blockmasks should form; a goal is to reduce wire delay in timing critical paths. The problem is formulated using a graph: a vertex corresponds to wire segment with its maximum length for widening as a vertex weight; an edge represents a potential conflict between two candidate wire segments that we wish to widen. A maximum weight independent set corresponds to an ideal solution. For a few circuits that we test, wire resistance of timing critical nets is reduced by 18.5% on average, which leads to 9.9% reduction in clock period.

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