Soft Error-Aware Architectural Exploration for Designing Reliability Adaptive Cache Hierarchies in Multi-Cores

Arun Subramaniyan1, Semeen Rehman2,a, Muhammad Shafique3, Akash Kumar2 and Jörg Henkel4
1University of Michigan-Ann Arbor, USA.
2Chair for Processor Design, TU Dresden, Germany.
3Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria.
4Chair for Embedded Systems, Karlsruhe Institute of Technology, Germany


Mainstream multi-core processors employ large multi-level on-chip caches making them highly susceptible to soft errors. We demonstrate that designing a reliable cache hierarchy requires understanding the vulnerability interdependencies across different cache levels. This involves vulnerability analyses depending upon the parameters of different cache levels (partition size, line size, etc.) and the corresponding cache access patterns for different applications. This paper presents a novel soft error-aware cache architectural space exploration methodology and vulnerability analysis of multi-level caches considering their vulnerability interdependencies. Our technique significantly reduces exploration time while providing reliability-efficient cache configurations. We also show applicability/benefits for ECC-protected caches under multi-bit fault scenarios.

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