A Static-Placement, Dynamic-Issue Framework for CGRA Loop Accelerator

Zhongyuan Zhao1,a, Weiguang Sheng1, Weifeng He1, ZhiGang Mao1 and Zhaoshi Li2
1Department of Micro/NaNo Electronics, Shanghai Jiao Tong University, Shanghai, China.
2Institution of Micro Electronics, Tsinghua University, Beijing, China


This paper presents a static-placement, dynamicissue (SPDI) framework for the coarse-grained reconfigurable architecture (CGRA) in order to tackle the inefficiencies of the static-issue, static-placement (SISP) CGRA. This framework includes the compiler that statically places the operations and hardware design, a SPDI CGRA, that automatically schedule the operations. We stress on introducing the SPDI CGRA in this paper. This newly designed hardware model adds the token buffer, which is capable of automatically scheduling the operations inside processing elements (PE), along with a router network that can effectively transform and control data flow among the PE array. This design lets the hardware share the responsibility for the compiler, making them cooperate to deal with the issuing, placement and routing problem. Evaluation of our study shows that our framework can reach on average 1.28, 1.30 and 1.33 higher than three state-of-the-art SISP CGRA using REGIMap, RS compile flow and the EPIMap approaches respectively. The area overhead is nearly 0.93% per token buffer entry for each PE relative to SISP CGRA.

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