Testing Microfluidic Fully Programmable Valve Arrays (FPVAs)
Chunfeng Liu1,5,a, Bing Li1,b, Bhargab B. Bhattacharya2, Krishnendu Chakrabarty3,5,d, Tsung-Yi Ho4,5,e and Ulf Schlichtmann1,c
1Institute for Electronic Design Automation, Technical University of Munich, Germany.
achunfeng.liu@tum.de
bb.li@tum.de
culf.schlichtmann@tum.de
2Indian Statistical Institute, Kolkata, India.
bhargab@isical.ac.in
3Department of ECE, Duke University, Durham, NC, USA.
dkrish@ee.duke.edu
4National Tsing Hua University, Hsinchu, Taiwan.
etyho@cs.nthu.edu.tw
5Institute for Advanced Study, Technical University of Munich, Germany
ABSTRACT
Fully Programmable Valve Array (FPVA) has emerged as a new architecture for the next-generation flow-based microfluidic biochips. This 2D-array consists of regularly-arranged valves, which can be dynamically configured by users to realize microfluidic devices of different shapes and sizes as well as interconnections. Additionally, the regularity of the underlying structure renders FPVAs easier to integrate on a tiny chip. However, these arrays may suffer from various manufacturing defects such as blockage and leakage in control and flow channels. Unfortunately, no efficient method is yet known for testing such a general-purpose architecture. In this paper, we present a novel formulation using the concept of flow paths and cut-sets, and describe an ILP-based hierarchical strategy for generating compact test sets that can detect multiple faults in FPVAs. Simulation results demonstrate the efficacy of the proposed method in detecting manufacturing faults with only a small number of test vectors.
