Tunnel FET Based Refresh-Free-DRAM
Navneet Gupta1,2, Adam Makosiej2, Andrei Vladimirescu1, Amara Amara1 and Costin Anghel1
1MINARC Laboratory, Institut Superieur d'Electronique de Paris (ISEP) France.
anavneet.gupta@isep.fr
bcostin.anghel@isep.fr
2LETI, Commissariat à l'Energie Atomique et aux Energies Alternatives (CEA-LETI) France
ABSTRACT
A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275μm2 is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal.
Keywords: Tunnel FET, DRAM, eDRAM, Metal-Insulator-Metal (MIM) capacitors.
