Fast Architecture-Level Synthesis of Fault-Tolerant Flow-Based Microfluidic Biochips

Wei-Lun Huang1, Ankur Gupta2, Sudip Roy2, Tsung-Yi Ho1 and Paul Pop3
1Dept. of Computer Science, National Tsing Hua University, Taiwan.
2CoDA Laboratory, Dept. of Computer Science & Engineering, Indian Institute of Technology Roorkee, India.
3DTU Compute, Technical University of Denmark, Denmark.


Microfluidic-based lab-on-a-chips have emerged as a popular technology for implementation of different biochemical test protocols used in medical diagnostics. However, in the manufacturing process or during operation of such chips, some faults may occur that leads to damage of the chip, which in turn results in wastage of expensive reagent fluids. In order to make the chip fault-tolerant, the state-of-the-art technique adopts simulated annealing (SA) based approach to synthesize a fault-tolerant architecture. However, the SA method is time consuming and non-deterministic with over-simplified model that usually derive sub-optimal results. Thus, we propose a progressive optimization procedure for the synthesis of fault-tolerant flow-based microfluidic biochips. Simulation results demonstrate that proposed method is efficient compared to the state-of-theart techniques and can provide effective solutions in 88% (on average) less CPU time compared to state-of-the-art technique over three benchmark bioprotocols.

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