Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing
Shaodi Wanga, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili-Amiri, Kang L. Wang and Puneet Guptab
Department of Electrical Engineering, University of California, Los Angeles, CA 90095 USA.
ashaodiwang@ucla.edu
bpuneet@ucla.edu
ABSTRACT
In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machinelearning algorithm). 3X - 37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.
Keywords: Non-volatile, Voltage-controlled magnetic tunnel junction, Negative differential resistance, Stochastic computing.
