A Thermally-Aware Energy Minimization Methodology for Global Interconnects
Soheil Nazar Shahsavania, Alireza Shafaeib, Shahin Nazarianc and Massoud Pedramd
Department of Electrical Engineering, University of Southern California Los Angeles, CA 90089 USA.
anazarsha@usc.edu
bshafaeib@usc.edu
cshahin@usc.edu
dpedram@usc.edu
ABSTRACT
As a result of the Temperature Effect Inversion (TEI) in FinFET-based designs, gate delays decrease with the increase of temperature. In contrast, the resistive characteristic and hence delay of global interconnects increase with the temperature. However, as shown in this paper, if buffers are judiciously inserted in global interconnects, the buffer delay decrease is more pronounced than the interconnect delay increase, resulting in an overall performance improvement at higher temperatures. More specifically, this work models the delay of buffer-inserted global interconnects vs. temperature in order to derive the optimal number and size of buffers for a given interconnect length and temperature. Furthermore, the paper addresses the problem of minimizing the buffered interconnect energy consumption by changing the supply voltage level or FinFET threshold voltage, and also presents a temperature-aware optimization policy for solving this problem. Simulation results show average interconnect energy savings of 16% with no performance penalty for five different benchmarks implemented on a 14nm FinFET technology.
