An Energy-Efficient Memory Hierarchy for Multi-Issue Processors
Tiago Josta, Gabriel Nazarb and Luigi Carroc
Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil.
attjost@inf.ufrgs.br
bglnazar@inf.ufrgs.br
ccarro@inf.ufrgs.br
ABSTRACT
Embedded processors must rely on the efficient use of instruction-level parallelism to answer the performance and energy needs of modern applications. However, a limiting factor to better use available resources inside the processor concerns memory bandwidth. Adding extra ports to allow for more data accesses drastically increases costs and energy. In this paper, we present a novel memory architecture system for embedded multi-issue processors that can overcome the limited memory bandwidth without adding extra ports to the system. We combine the use of software-managed memories (SMM) with the data cache to provide a system with a higher throughput without increasing the number of ports. Compiler-automated code transformations minimize the effort of programmers to benefit from the proposed architecture. Our experimental results show an average speedup of 1.17x, while consuming 69% less dynamic energy and on average 74.7% lower energy-delay product regarding data memory in comparison to a baseline processor.
Keywords: Very long instruction word processor, Bandwidth, Memory architecture, Software-managed memory, Compiler.
