Endurance Management for Resistive Logic-In-Memory Computing Architectures

Saeideh Shirinzadeh1, Mathias Soeken2, Pierre-Emmanuel Gaillardon3, Giovanni De Micheli1 and Rolf Drechsler1,4
1Department of Mathematics and Computer Science, University of Bremen, Germany
2Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
3Electrical and Computer Engineering Department, University of Utah, Salt Lake City, UT, USA
4Cyber-Physical Systems, DFKI GmbH, Bremen, Germany


Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

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