Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits

Michael Raitza1, Akash Kumar1, Marcus Völp2, Dennis Walter3, Jens Trommer4,c, Thomas Mikolajick4,d and Walter M. Weber4,e
1Processor Design Group, Technische Universität Dresden, Dresden, Germany.
2University of Luxembourg, Luxembourg.
3Technische Universität Dresden, Dresden, Germany.
4Namlab gGmbH, Dresden, Germany. cjens.trommer@namlab.de, dthomas.mikolajick@namlab.de, ewalter.weber@namlab.de


Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16%, despite larger size of the individual transistor, and improve circuit speed by 26%.

Keywords: Reconfigurable transistor, Silicon nanowire transistor, RFET, TIGFET, FET, Conditional sum adder, Conditional carry adder, Reconfigurable circuit, Reconfiguration.

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