Design Space Exploration of FPGA-Based Accelerators with Multi-Level Parallelism

Guanwen Zhong1,a, Alok Prakash2, Siqi Wang1,b, Yun Liang3, Tulika Mitra1,c and Smail Niar4
1School of Computing, National University of Singapore.
2SCSE, Nanyang Technological University.
3School of EECS, Peking University, China.
4LAMIH, University of Valenciennes, France.


Applications containing compute-intensive kernels with nested loops can effectively leverage FPGAs to exploit fineand coarse-grained parallelism. HLS tools used to translate these kernels from high-level languages (e.g., C/C++), however, are inefficient in exploiting multiple levels of parallelism automatically, thereby producing sub-optimal accelerators. Moreover, the large design space resulting from the various combinations of fineand coarse-grained parallelism options makes exhaustive design space exploration prohibitively time-consuming with HLS tools. Hence, we propose a rapid estimation framework, MPSeeker, to evaluate performance/area metrics of various accelerator options for an application at an early design phase. Experimental results show that MPSeeker can rapidly (in minutes) explore the complex design space and accurately estimate performance/area of various design points to identify the near-optimal (95.7% performance of the optimal on average) combination of parallelism options.

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