Revamping Timing Error Resilience to Tackle Choke Points at NTC Systems
Aatreyi Bala, Shamik Sahab, Sanghamitra Royc and Koushik Chakrabortyd
USU BRIDGE LAB, Electrical and Computer Engineering, Utah State University.
abal.aatreyi@gmail.com
bshmk_saha@yahoo.co.in
ckoushik.chakraborty@usu.edu
dsanghamitra.roy@usu.edu
ABSTRACT
Process variation is a conspicuous predicament for sub-micron VLSI circuits. In this paper, we illustrate ``choke points'' as a vital consequence of process variation in the Near Thresh-old Computing (NTC) domain. Choke points are process variation affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths post-fabrication. To mitigate the timing errors induced thereby, we propose Dynamic Choke Sensing (DCS). This technique senses the timing error causing opcode sequences, and uses the knowledge to prevent similar sequences from causing errors in future. Our scheme provides 25%-160% improvement in performance and 50%-90% improvement in energy efficiency as compared to contemporary timing error mitigation schemes, with minimal area and power overheads.
