Application Performance Improvement By Exploiting Process Variability On FPGA Devices
Konstantinos Maragos1,a, George Lentaris1,b, Dimitrios Soudris1,c, Kostas Siozios2,d,e and Vasilis F. Pavlidis3
1School of ECE, National Technical University of Athens.
akomaragos@microlab.ntua.gr
bglentaris@microlab.ntua.gr
cdsoudris@microlab.ntua.gr
dksiop@microlab.ntua.gr
2Department of Physics, Aristotle Univ. of Thessaloniki.
eksiop@auth.gr
3School of Computer Science, The Univ. of Manchester.
pavlidis@cs.man.ac.uk
ABSTRACT
Process variability is known to be increasing with technology scaling in IC fabrication, thereby degrading the overall performance of the manufactured devices. The current paper focuses on the variability effect in FPGAs and the possibility to boost the performance of each device at run-time, after fabrication, based on the individual characteristics of this device. First, we develop a sensing infrastructure involving a wide network of customized ring oscillators to measure intra-chip and inter-chip variability in 28nm FPGAs, i.e., in eight Xilinx Zynq XC7Z020T-1CSG324 devices. Second, we develop a closed-loop framework based on dynamic reconfiguration of clock tiles, I/O data sniffing, HW/SW communication, and verification with test vectors, to dynamically increase the operating frequency in Zynq while preserving its correctness. Our results show intra-chip variability in the area of 5.2% to 7.7% and inter-chip variability up to 17%. Our framework improves the performance of example FIR designs by up to 90.3% compared to the SW tool reports and shows speed difference among devices by up to 12.4%.
