Mitigation of Sense Amplifier Degradation Using Input Switching
Daniël Kraak1,a, Innocent Agbo1,b, Mottaqiallah Taouil1,c, Said Hamdioui1,d, Pieter Weckx2,3,e, Stefan Cosemans2, Francky Catthoor2,3,f and Wim Dehaene3,g
1Delft University of Technology, Faculty of Electrical Engineering, Mathematics and CS, Mekelweg 4, 2628 CD Delft, The Netherlands.
aD.H.P.Kraak@tudelft.nl
bI.O.Agbo@tudelft.nl
cM.Taouil@tudelft.nl
dS.Hamdioui@tudelft.nl
2imec vzw., Kapeldreef 75, B-3001, Leuven, Belgium.
ePieter.Weckx@imec.be
fFrancky.Catthoor@imec.be
3Katholieke Universiteit Leuven, ESAT, Belgium.
gwim.dehaene@esat.kuleuven.be
ABSTRACT
To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worstcase scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ~ 40% and ~ 10%, respectively, depending on the stress conditions (temperature, voltage, workload).
Keywords: Mitigation, Offset voltage, Zero-time variability, Run-time variability, SRAM sense amplifier, Sensing delay.
