Analyzing the Effects of Peripheral Circuit Aging of Embedded SRAM Architectures
Josef Kinseher1,2, Leonhard Heiß1 and Ilia Polian2
1Intel Deutschland, 85579 Neubiberg, Germany.
ajosef.kinseher@intel.com
bleonhard.heiss@intel.com
2University of Passau, 94032 Passau, Germany.
ilia.polian@uni-passau.de
ABSTRACT
Modern System-on-Chips rely heavily on the performance of their embedded memories which are also most susceptible to the increasing reliability challenges of today's nanoscale technology nodes. However, in contrast to memory core-cells, the effects of transistor aging inside the peripheral logic of SRAM architectures have received little attention. This study works out how BTI and HCI induced wear-out of the peripheral SRAM circuitry impacts various performance metrics of an industrially used memory library. We show that the degradation of the peripheral logic is the dominant driver for access speed loss while it tends to slightly lower memory read margin and lead to minor improvements of write margin. We furthermore show that in terms of access time margin the degradation of SRAM control circuitry counteracts aging effects inside core-cells and sense amplifiers. Surprisingly, wear-out of peripheral circuitry can even improve access time margin in case when the relative magnitude of PBTI is much lower compared with NBTI. Based on the example of an embedded memory library, this study further underlines the importance to analyze aging mechanisms at system level rather than for its individual interacting sub-circuits.
