MeSAP: A Fast Analytic Power Model for DRAM Memories

Sandeep Poddar1, Rik Jongerius1, Leandro Fiorin1, Giovanni Mariani1, Gero Dittmann2, Andreea Anghel2 and Henk Corporaal3
1IBM Research, The Netherlands
2IBM Research - Zurich, Switzerland
3Eindhoven University of Technology, The Netherlands


The design of an energy-efficient memory subsystem is one of the key issues that system architects face today. To achieve this goal, architects usually rely on system simulators and trace-based DRAM power models. However, their long execution time makes the approach infeasible for the designspace exploration of next-generation exascale computing systems. Analytic models, in contrast, are orders of magnitude faster.
In this paper, we propose a new analytic memory-scheduleragnostic power model for DRAM, henceforth referred to as MeSAP. Similarly to state-of-the-art trace-based approaches, our analytic model achieves an average error of 20%, while being an order of magnitude faster. Furthermore, we integrate MeSAP into an analytic performance model of general-purpose processors and show its applicability to the design of a computing system targeting scientific image processing applications.

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