VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories
Sarath Mohanachandran Naira, Rajendra Bishnoib, Mohammad Saber Golanbaric, Fabian Oborild and Mehdi B. Tahoorie
Chair of Dependable Nano Computing (CDNC), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany.
asarath.nair@kit.edu
bgolanbari@kit.edu
crajendra.bishnoi@kit.edu
dfabian.oboril@kit.edu
emehdi.tahoori@kit.edu
ABSTRACT
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate to replace CMOS based on-chip memories due to its advantages such as non-volatility, high density and scalability. However, its stochastic switching and higher sensitivity to process variation compared to CMOS memories can significantly affect its performance, energy and reliability. Although a few works exist which analyze the impact of process variation at the bit-cell level, such analysis at the system level is missing. We have bridged this gap in our work. Specifically, we quantify the effect of stochasticity and process variations from the cell-level to the overall memory system and perform a variation-aware memory configuration optimization for energy or performance while meeting reliability constraints. Our system-level variation-aware framework has been built on top of the well-known NVSim engine. The results show that our framework can provide more realistic margins and the optimized variation-aware memory configuration could be significantly different from the conventional framework.
