Recovery-Aware Proactive TSV Repair for Electromigration in 3D ICs
Shengcheng Wang1,a, Hongyang Zhao2,c, Sheldon X.-D. Tan1,b and Mehdi B. Tahoori2,d
1Chair of Dependable Nano Computing (CDNC), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany.
ashengcheng.wang@kit.edu
bmehdi.tahoori@kit.edu
2Department of Electrical and Computer Engineering, University of California, Riverside, CA, USA.
chzhao@ece.ucr.edu
dstan@ece.ucr.edu
ABSTRACT
Electromigration (EM) becomes a major reliability concern in three-dimensional integrated-circuits (3D ICs). To mitigate this problem, a typical solution is to use TSV redundancy in a reactive manner, maintaining the operability of a 3D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this work, we explore an alternative, more preferred approach to enhance the EM-related lifetime reliability of TSV grid, in which redundancy is used proactively to allow non-faulty TSVs to be temporarily deactivated. In this way, EM wear-out can be reversed by exploiting its recovery property. Applied to 3D benchmark designs, the recovery-aware proactive repair approach increases EM-related lifetime reliability (measured in mean-time-to-failure) of the entire TSV grid by up to 12X relative to the conventional reactive method, with less area overhead.
