A Log-aware Synergized Scheme for Page-Level FTL Design
Chu Li1,a, Dan Feng1,b, Yu Hua1,c, Fang Wang1,d, Chuntao Jiang2 and Wei Zhou1,e
1Wuhan National Lab for Optoelectronics, School of Computer, Huazhong University of Science and Technology, Wuhan, China.
alichu@hust.edu.cn
bdfeng@hust.edu.cn
ccsyhua@hust.edu.cn
dwangfang@hust.edu.cn
emmbl@hust.edu.cn
2Illinois Institute of Technology, Chicago, IL, United States.
chuntjiang@gmail.com
ABSTRACT
NAND flash-based Solid State Drives (SSDs) employ the Flash Translation Layer (FTL) to perform logical-to-physical address translation. Modern page-level FTLs selectively cache the address mappings in the limited SRAM while storing the mapping table in flash pages (called translation pages). However, many extra accesses to the translation pages are required for address translation, which decreases the performance and lifetime of an SSD. In this paper, we propose a Log-aware Synergized scheme for page-level FTL to reduce the extra overheads, called LSFTL. The contribution of LSFTL consists of two key elements: (i) By exploiting the partial programmability of SLC flash, in-place logging decreases garbage collection overhead via reserving a small portion of each translation page as a logging area to hold multiple updates to the entries of that translation page. (ii) Log-aware flush back reduces the number of translation page updates by evicting multiple dirty cache lines that share the same translation page in a single transaction. Extensive experimental results of trace-driven simulations show that LSFTL decreases the system response time by 39.40% on average, and up to 58.35%, and reduces the block erase count by 37.55% on average, and up to 39.99%, compared to the well-known DFTL.
