Enhancing Analog Yield Optimization for Variation-aware Circuits Sizing
Ons Lahiouela, Mohamed H. Zakib and Sofiène Taharc
Dept. of Electrical and Computer Engineering, Concordia University, Montréal, Québec, Canada.
alahiouel@ece.concordia.ca
bmzaki@ece.concordia.ca
ctahar@ece.concordia.ca
ABSTRACT
This paper presents a novel approach for improving automated analog yield optimization using a two step exploration strategy. First, a global optimization phase relies on a modified Lipschitizian optimization to sample the potential optimal subregions of the feasible design space. The search locates a design point near the optimal solution that is used as a starting point by a local optimization phase. The local search constructs linear interpolating surrogate models of the yield to explore the basin of convergence and to rapidly reach the global optimum. Experimental results show that our approach locates higher quality design points in terms of yield rate within less run time and without affecting the accuracy.
