Architectural Evaluations on TSV Redundancy for Reliability Enhancement
Yen-Hao Chen1,a, Chien-Pang Chiu1,b, Russell Barnes2 and TingTing Hwang1,c
1Department of Computer Science, National Tsing Hua University, Taiwan.
ayhchen@cs.nthu.edu.tw
bs103062556@m103.nthu.edu.tw
ctingting@cs.nthu.edu.tw
2Department of Electrical and Computer Engineering, University of California at Santa Barbara, United States.
russell@ece.ucsb.edu
ABSTRACT
Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome the scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can be transmitted through dies vertically. However, researchers have noticed that the aging effect due to the electormigration (EM) may result in faulty TSVs and affect the chip lifetime [1]. Several redundant TSV architectures have been proposed to address this issue. By replacing the faulty TSV with redundant TSVs which are added at design time, chips can achieve better reliability and longer lifetime. In this paper, we will study the tradeoff of various redundant TSV architectures in terms of effectiveness and cost. To allow the measurement of reliability more realistically, we propose a new standard, repair rate, to appraise the redundant TSV architectures. Moreover, to design a more flexible and efficient structure, we enhance the ring-based design [2] that can adjust the size of the TSV block and TSV redundancy.
