Modeling Instruction Cache and Instruction Buffer for Performance Estimation of VLIW Architectures using Native Simulation
Omayma Matoussia and Frédéric Pétrotb
TIMA Laboratory, Univ. Grenoble Alpes/CNRS/Grenoble INP, F-38000, Grenoble, France.
aomayma.matoussi@imag.fr
bfrederic.petrot@imag.fr
ABSTRACT
In this work, we propose an icache performance estimation approach that focuses on a component necessary to handle the instruction parallelism in a very long instruction word (VLIW) processor: the instruction buffer (IB). Our annotation approach is founded on an intermediate level nativesimulation framework. It is evaluated with reference to a cycle accurate instruction set simulator leading to an average cycle count error of 9.3% and an average speedup of 10.
