Automatic Place-and-Route of Emerging LED-Driven Wires within a Monolithically-Integrated CMOS+III-V Process

Tushar Krishna1,2, Arya Balachandran1,3, Siau Ben Chiah1,3 Li Zhang1, Bing Wang1, Cong Wang1,3, Kenneth Lee Eng Kian1, Jurgen Michel1 and Li-Shiuan Peh1,4
1SMART LEES, Singapore
2Georgia Institute of Technology, USA
3NTU, Singapore
4NUS, Singapore


We leverage a recently demonstrated CMOS compatible IIIV and Si monolithic integrated process to design photonic links comprising LEDs and photodiodes, as direct replacements for onchip electrical wires. To enable VLSI-scale design of chips with such LED links, we create a library of opto-electronic standard cells, and model waveguides as traditional metal layers. This lets us integrate LED links into a commercial place-and-route tool, which treats them as electrical cells and wires for the most part, reducing design effort. We also add support for automated replacement of electrical nets with LED links.
We find that LED-interconnect based designs substantially lower energy consumption vs. electrical copper wires ( ~ 39% reduction in the Network-on-Chip, ~ 27% reduction within a processor core) while achieving the same latency and bandwidth, demonstrating the promise of LED on-chip interconnects.

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