Architecting High-Speed Command Schedulers for Open-Row Real-Time SDRAM Controllers
Leonardo Eccoa and Rolf Ernstb
Institute of Computer and Network Engineering - TU Braunschweig, Germany.
aecco@ida.ing.tu-bs.de
bernst@ida.ing.tu-bs.de
ABSTRACT
As SDRAM modules get faster and their data buses wider, researchers proposed the use of the open-row policy in command schedulers for real-time SDRAM controllers. While the real-time properties of such schedulers have been thoroughly investigated, their hardware implementation was not. Hence, in this paper, we propose a highly-parallel and multi-stage architecture that implements a state-of-the open-row real-time command scheduler. Moreover, we evaluate such architecture from the hardware overhead and performance perspectives.
