Superword Level Parallelism aware Word Length Optimization

Ali Hassan El Moussawia and Steven Derrienb
Université de Rennes 1, Rennes, France.


Many embedded processors do not support floatingpoint arithmetic in order to comply with strict cost and power consumption constraints. But, they generally provide support for SIMD as a mean to improve performance for little cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient exploitation of SIMD data-path. To reduce time-to-market, automatic SIMDization - such as superword level parallelism (SLP) extraction - and float-to-fixed-point conversion methodologies have been proposed. In this paper we show that applying these transformations independently is not efficient. We propose a SLPaware word length optimization algorithm to jointly perform float-to-fixed-point conversion and SLP extraction.We implement the proposed approach in a source-to-source compiler framework and evaluate it on several embedded processors. Experimental results illustrate the validity of our approach.

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