An Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart

Weiwei Jiang1,a, Davide Bertozzi2,c, Gabriele Miorandi2,d, Steven M. Nowick1,b, Wayne Burleson3 and Greg Sadowski3
1Columbia University, New York, NY, USA.
2University of Ferrara, Ferrara, Italy.
3Advanced Micro Devices, Inc., Boxborough, MA, USA.


An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynch-ronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained.

Full Text (PDF)