A Comprehensive Study of Monolithic 3D Cell on Cell Design Using Commercial 2D Tool
O. Billoint1,a, H. Sarhan1, I. Rayane2, M. Vinet1, P. Batude1, C. Fenouillet-Beranger1, O. Rozeau1, G. Cibrario1, F. Deprat1, A. Fustier1, J.-E. Michallet1, O. Faynot1, O. Turkyilmaz1, J.-F. Christmann1, S. Thuries1 and F. Clermidy1
1Univ. Grenoble Alpes, F-38000 Grenoble, France, CEA, LETI, MINATEC Campus, F-38054 Grenoble, France.
2Mentor Graphics, 110 rue Blaise Pascal, Montbonnot-Saint-Martin, France
In this paper we present a methodology allowing an emulated-3D two tiers physical implementation of any design using 2D commercial tools. Place and Route is achieved through similar steps as required by 2D designs: pre clock tree synthesis (including placement), clock tree synthesis and routing; to which we added a folding step in order to emulate the 3D placement. Routing of both tiers in parallel using inter-tier metal layers is made possible by modifying input files of the tools. Our study covers power supply network on both tiers, forbidden inter-tier via on active placement and inter-tier back end flavors in order to refine quality of results. Benchmark results on two tiers 3D Monolithic integration have been done on several IPs (microcontroller, reconfigurable FFT and LDPC) using as reference ST 28nm FDSOI technology and show the correlation between cell density, routing congestion, wire length, operating frequency and power consumption. To our knowledge, this paper is the first one to evaluate monolithic 3D physical implementation using full 3D Back End description and taking into account power supply distribution on both tiers.
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