doi: 10.7873/DATE.2015.0392

Synergistic Use of Multiple On-Chip Networks for Ultra-Low Latency and Scalable Distributed Routing Reconfiguration

Marco Balboni^1,a, José Flich² and Davide Bertozzi^1,b

¹ENDIF - MPSoC Research Group, University of Ferrara, Italy.

^amarco.balboni@unife.it ^bdavide.bertozzi@unife.it

²GAP - Parallel Architectures Group Universidad Politécnica de Valéncia, Spain.

jflich@gap.upv.es

ABSTRACT

Extending the principle of partially good die allowance to manycore processors, and testing them over time to detect the onset of permanent faults, are only feasible through proper support in the on-chip interconnection network. In fact, this implies the ability to reconfigure the routing algorithm at runtime to reflect changes in network topologies. Current literature cannot avoid a large hardware and/or software overhead when tackling this challenge. This paper exploits the existence of multiple physical networks in industry-relevant manycore processors in a synergistic way, for the sake of fast and scalable distributed reconfiguration of the routing function at runtime.

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Synergistic Use of Multiple On-Chip Networks for Ultra-Low Latency and Scalable Distributed Routing Reconfiguration

Marco Balboni1,a, José Flich2 and Davide Bertozzi1,b

1ENDIF - MPSoC Research Group, University of Ferrara, Italy.

2GAP - Parallel Architectures Group Universidad Politécnica de Valéncia, Spain.

ABSTRACT

Marco Balboni^1,a, José Flich² and Davide Bertozzi^1,b

¹ENDIF - MPSoC Research Group, University of Ferrara, Italy.

²GAP - Parallel Architectures Group Universidad Politécnica de Valéncia, Spain.