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addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.
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Chair: Frederic Mallet, University of Nice Sophia Antipolis, FR, Contact
Co-Chair: Gianluca Palermo, Politecnico di Milano, IT, Contact
Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; modeling of system adaptivity; time and performance modeling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.
Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact
Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact
High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.
Chair: Graziano Pravadelli, University of Verona, IT, Contact
Co-Chair: Avi Ziv, IBM Research - Haifa, IL, Contact
Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.
Chair: Alessandro Cimatti, Fondazione Bruno Kessler, IT, Contact
Co-Chair: Anna Slobodova, Centaur Technology, US, Contact
Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.
Chair: Manuel Barragan, TIMA Laboratory, FR, Contact
Co-Chair: mphlin 
nctu [dot] edu [dot] tw, Contact
tum [dot] de, Contact ece [dot] ucsb [dot] edu, ContactAnalog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics; verification and simulation of analog and mixed-signals.
Chair: Ilia Polian, University of Stuttgart, DE, Contact
Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact
st [dot] com, Contact nxp [dot] com, ContactHardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW Trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; interplay between machine learning and security.
Chair: Romain Lemaire, CEA-Leti, FR, Contact
Co-Chair: Li-Shiuan Peh, Professor, National University of Singapore, SG, Contact
Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, NoC and communication-centric design, including: topology, switching, routing and flow control; communication-aware frameworks for Quality-of-Service, security, robustness, power, variability and thermal management; design space exploration frameworks and programming models for communication-centric design; interconnects for domain-specific applications (high performance computing, in-memory computing, machine learning, etc.); design of interconnects using alternative/emerging technologies (photonics, 2.5D/3D, quantum computing, etc.).
Chair: Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact
Co-Chair: Olivier Sentieys, INRIA, FR, Contact
inria [dot] fr, Contact sfu [dot] ca, Contact ece [dot] ubc [dot] ca, ContactArchitectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.
Chair: Andrea Calimera, Politecnico di Torino, IT, Contact
Co-Chair: Pascal Vivet, CEA-Leti, FR, Contact
st [dot] com, ContactTheories, tools and methodologies to design electronic systems with low power consumption, high energy efficiency, and correct thermal behavior, ranging from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centers and cloud computing). Topics of interest include: solutions applicable to all layers of design (hardware, software and any cross-layers) with emphasis on power modeling and optimization, temperature modeling and prediction, thermal-power-aware optimization, energy-aware design, battery-aware design, including thermal-power-aware optimization for application specific designs (e.g. AI, ML, etc), smart management of heterogeneous energy-sources, energy harvesting for cyber-physical systems.
Chair: Lukas Sekanina, Brno University of Technology, CZ, Contact
Co-Chair: Tajana Rosing, University of California, San Diego, US, Contact
Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking.
Chair: Philip Brisk, University of California, Riverside, US, Contact
Co-Chair: Suhaib A. Fahmy, University of Warwick, GB, Contact
Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.
Chair: Luis Miguel Silveira, INESC-ID/IST, PT, Contact
Co-Chair: Mathias Soeken, Integrated System Laboratory – EPFL, CH, Contact
gmail [dot] com, ContactCombinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.
Chair: Elena Gnani, Università di Bologna, IT, Contact
Co-Chair: Subhasish Mitra, Stanford University, US, Contact
illinois [dot] edu, Contact imec [dot] be, Contact tuwien [dot] ac [dot] at, ContactModeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).
Chair: Shahar Kvatinsky, Technion, IL, Contact
Co-Chair: Chengmo Yang, University of Delaware, US, Contact
utdallas [dot] edu, Contact alibaba-inc [dot] com, ContactModeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.
is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.
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Chair: Baris Aksanli, San Diego State University, US, Contact
Co-Chair: Jungwook Choi, Hanyang University, KR, Contact
Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.
Chair: Ulrike Thomas, Technical University of Chemnitz, DE, Contact
Co-Chair: Federica Ferraguti, University of Modena and Reggio Emilia, IT, Contact
Bringing together robotics and machine learning concepts requires research and development efforts in interdisciplinary domains. With Industry 4.0 and its goal of adding utility value through data analytics and optimiztion, the Topic "Robotics and Industry 4.0" will remain at the core of the value creation chain during the next decade. The topic covers the field of robotics on topics from sensors and sensory interpretations to kinematics in motion planning, from distributed software concepts for data collection and analysis to large-scale machine learning algorithms, and sensor-based robot and machine control to safe human-robot interaction concepts.
Chair: Sebastian Steinhorst, TUM, DE, Contact
Co-Chair: David Boyle, Imperial College London, GB, Contact
Design experiences for automotive systems, energy-neutral embedded systems, smart energy systems (from uW to microgrid), and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits; MEMS; integrated sensors and transducers; RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; battery management and E/E architecture for electric vehicles; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.
Chair: Ioannis Papaefstathiou, School of Electrical and Computer Engineering, Aristotle University of Thessaloniki, GR, Contact
Co-Chair: Daniela De Venuto, Politecnico di Bari, IT, Contact
Design experiences covering the use of body area networks, assistive and wearable technologies, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.
Chair: Lionel Torres, University of Montpellier, FR, Contact
Co-Chair: Cambou Bertrand, Northern Arizona University, US, Contact
Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.
Chair: Antonio Miele, Politecnico di Milano, IT, Contact
Co-Chair: Gilles Sassatelli, LIRMM CNRS / University of Montpellier 2, FR, Contact
Self-adaptive systems, algorithms and techniques for run-time decision-making targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Topics of interests include: adaptive strategies for runtime resource management; application, design and tuning of machine learning techniques for offline and/or online modeling, prediction/forecasting and control of self-adaptive systems; hybrid offline/online techniques for online decision-making; context-aware adaptation strategies and mechanisms; application of diverse data mining, modeling and optimization techniques (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive systems possibly based on machine learning techniques.
Chair: Robert Wille, Johannes Kepler University Linz, AT, Contact
Co-Chair: Michael Niemier, University Of Notre Dame, US, Contact
purdue [dot] edu, Contact tsinghua [dot] edu [dot] cn, Contact gmail [dot] com, ContactApplications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).
Chair: Norbert Wehn, University of Kaiserslautern, DE, Contact
Co-Chair: Nicolas Ventroux, CEA, LIST, FR, Contact
Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.
covers all test, design-for-test, reliability, and designfor-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.
Track Chair:
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Chair: Arnaud Virazel, LIRMM, FR, Contact
Co-Chair: Bram Kruseman, NXP Semiconductors, NL, Contact
Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.
Chair: Patrick Girard, LIRMM, FR, Contact
Co-Chair: Bernd Becker, University of Freiburg, DE, Contact
Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, accelerators, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.
Chair: Ramon Canal, UPC, ES, Contact
Co-Chair: Stefano Di Carlo, Politecnico di Torino, IT, Contact
Micro/architectures for fault-tolerant systems against permanent, transient and soft errors, including (but not limited to) processors, memories and accelerators; micro/architectural solutions for safety- and mission-critical systems; analysis and evaluation of reliability, availability and maintainability at micro/architectural level; hardware/software micro/architectural solutions for fault detection, recovery and aging mitigation.
Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY, Contact
Co-Chair: Georgios Karakonstantis, Queen's University Belfast, GB, Contact
HW and SW solutions for dependability at system level; system level error/fault modeling; dependability analysis and evaluation; reliable and fail-safe system design; system-level on-line test and functional safety; runtime system management for dependability; cross-layer solutions; application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.
Chair: Manuel Barragan, TIMA Laboratory, FR, Contact
Co-Chair: mphlin nctu [dot] edu [dot] tw, Contact
tum [dot] de, Contact ece [dot] ucsb [dot] edu, ContactAnalog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.
Chair: Ilia Polian, University of Stuttgart, DE, Contact
Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact
st [dot] com, Contact nxp [dot] com, ContactHardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation.
is devoted to the modelling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.
Track Chair: Valeria Bertacco, University of Michigan, US, Contact
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Chair: Dionisio de Niz, Carnegie Mellon University, US, Contact
Co-Chair: Liliana Cucu, INRIA, FR, Contact
control [dot] lth [dot] se, Contact bu [dot] edu, ContactReal-time performance modeling, analysis and empirical evaluation; Worst-case performance analysis techniques; Worst-case execution time analysis; Real-time schedulability of multicore systems; Mixed-Criticality scheduling; Real-time operating systems, microkernels and software; Use of hardware virtualization techniques in time critical applications, Power-aware real-time systems; Industrial case studies of real-time, networked and dependable systems; Adaptive real-time systems; Dependable systems including safety and criticality; Network control and QoS for embedded applications.
Chair: Tulika Mitra, National University of Singapore, SG, Contact
Co-Chair: Luca Carloni, Columbia University, US, Contact
gmail [dot] com, Contact microsoft [dot] com, Contact gmail [dot] com, ContactHardware and architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; approximate architectures for machine learning applications; learning from limited data sets; frameworks for probabilistic and deep learning programming; safe and secure machine learning; novel neural networks architectures and concepts for embedded computing; case studies of machine learning applications implemented on embedded systems.
Chair: Yliès Falcone, Univ. Grenoble Alpes, Inria, FR, Contact
Co-Chair: Todd Austin, University of Michigan, US, Contact
Verification techniques for embedded ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as security, timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems. Security attacks, protection and analysis of embedded systems' hardware and software.
Chair: Sara Vinco, Politecnico di Torino, IT, Contact
Co-Chair: Borzoo Bonakdarpour, Iowa State University, US, Contact
Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; Real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.
Chair: Shiyan Hu, Michigan Technological University, US, Contact
Co-Chair: Davide Quaglia, University of Verona, IT, Contact
Modeling, design, verification, validation and optimization of Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things; safety and security aspects in CPS; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids); cognitive control for CPS; networked and switched control systems (e.g., control/architecture co-design and architecture-aware controller synthesis).