Date: Wednesday 21 March 2018
Time: 17:00 - 18:30
Location / Room: Konf. 3
Chair:
Doris Keitel-Schulz, Infineon Technologies, DE
Co-Chair:
Norbert Wehn, University of Kaiserslautern, DE
This session covers industrial experiences from technologies such as NBTI mitigation and adaptive volatge scaling to system level aspects including safety-critical applications and IoT security.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 8.5.1 | NBTI AGED CELL REJUVENATION WITH BACK BIASING AND RESULTING CRITICAL PATH REORDERING FOR DIGITAL CIRCUITS IN 28NM FDSOI Speaker: Lorena Anghel, TIMA Labs, FR Authors: Ajith Sivadasan1, Riddhi Jitendrakumar Shah2, Vincent Huard3, Florian Cacho3 and Lorena Anghel4 1TIMA Labs & ST Microelectronics, FR; 2TIMA Labs, FR; 3STMicroelectronics, FR; 4Grenoble-Alpes University, FR Abstract Abstract— Increasing demands from Autonomous Driving and IoT markets are pushing the need for products with advanced CMOS nodes that guarantee a high level of performance and at the same time having to comply with industrial regulatory standards like ISO26262, AEC-Q100 etc. Implementation of NBTI & DiR Reliability models for 28nm FDSOI, developed in-house, are fundamental means to evaluate the reliability of digital IPs during the design phase. Process, Temperature, Voltage, Workload based Aging are mission profile parameters traditionally taken into account for design margin evaluations and critical path pruning. A precise critical path selection methodology is highly important considering the In-situ monitor Insertion and Critical Path Replica generation strategies to be applied to Runtime Reliability assessment with the vision to move towards dynamic wear out management solutions. This paper recommends the consideration of the silicon technology feature of back biasing as an important parameter while selecting Critical Paths for circuits fabricated with FDSOI process. Back biasing is an add-on feature of this technology with ABB (adaptive back biasing) techniques having been used to compensate for PVT variations or aimed at a gain in the overall digital circuit performance. This technique is now being increasingly applied to aging mitigation. The back-biasing gain for an aged digital IP is quantified while performing design stage Gate Level Analysis yielding interesting insights on its impact on the operational frequency determining critical path rankings. Keywords— NBTI, Back/Body Biasing, Aging, Critical Path, Reliability Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:15 | 8.5.2 | AN INDUSTRIAL CASE STUDY OF LOW COST ADAPTIVE VOLTAGE SCALING USING DELAY TEST PATTERNS Speaker: Mahroo Zandrahimi, TU Delft, NL Authors: Mahroo Zandrahimi1, Philippe Debaud2, Armand Castillejo2 and Zaid Al-Ars1 1Delft University of Technology, NL; 2STMicroelectronics, FR Abstract In deep sub-micron technologies, the increasing effect of process and environmental variations has lead chip manufacturers to use adaptive voltage scaling techniques in order to adapt operation parameters exclusively to each chip. The increasing effect of process variation is limiting the effectiveness of current chip monitoring approaches, such as on-chip performance monitor boxes (PMBs), which results in yield loss and high design margins, thus high power consumption. This paper proposes an alternative solution for adaptive voltage scaling using delay test patterns, which is able to eliminate the need for PMBs, and thus the long expensive characterization phase of tuning PMBs to each design, while improving the yield as well as power optimization. Results show, using an industrial grade 28nm FD- SOI library developed for low power devices, that delay testing for performance prediction reduces the inaccuracy down to 1.85%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 8.5.3 | A CASE STUDY FOR USING DYNAMIC PARTITIONING BASED SOLUTION IN VOLUME DIAGNOSIS Speaker: Wu Yang, Mentor, A Siemens Business, US Authors: Tao Wang1, Zhangchun Shi1, Junlin Huang1, Huaxing Tang2, Wu Yang2 and Junna Zhong3 1Hisilicon Technologies Co., Ltd, CN; 2Mentor, A Siemens Business, US; 3Mentor, A Siemens Business, CN Abstract Diagnosis driven yield analysis (DDYA) has been widely adopted for advanced technology node product yield ramp [1]. However gigantic design size and high pattern count demand intense computation resources to diagnose volume failure data, and the diagnosis throughput becomes the bottleneck for the DDYA flow. This paper presents a case study which uses the fully automated dynamic partitioning based diagnosis solution to dramatically improve the throughput. Experimental results based on real silicon data manufactured by a 16nm FinFET technology shows more than 3X reduction for memory footprint and more than 4X improvement for runtime, which eliminates the throughput bottleneck. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:45 | 8.5.4 | ON-LINE RF BUILT-IN SELF-TEST USING NOISE INJECTION AND TRANSMITTER SIGNAL MODULATION BY PHASE SHIFTER Speaker and Author: Jan Schat, NXP Semiconductors, DE Abstract For on-chip self-test of radar ICs, loopback test using a signal feedback path from transmitter to receiver is state-of-the-art. Usually, such a loopback test is performed periodically after a number of application-mode chirps. The traditional loopback test has two drawbacks, however: It is performed intermittent to the application mode, not within the application mode. Moreover, it cannot detect the case that the attenuation from transmitter to receiver becomes too low due to defects on the IC, or due to targets very near to the antennas. This paper proposes an advanced loopback test not intermittent to the application, but during application mode. That way, spurious defects like transient faults (also known as Single Event Upsets) can be detected; moreover, an error-prone plausibility check of the received signal is avoided. To detect receiver saturation due to near targets, modulating the transmitter output signal using a phase shifter is proposed. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 8.5.5 | NEURAL NETWORKS FOR SAFETY-CRITICAL APPLICATIONS - CHALLENGES, EXPERIMENTS AND PERSPECTIVES Speaker: Chih-Hong Cheng, fortiss, DE Authors: Chih-Hong Cheng1, Frederik Diehl2, Yassine Hamza2, Gereon Hinz2, Georg Nührenberg2, Markus Rickert2, Harald Ruess2 and Michael Troung-Le2 1fortiss - Landesforschungsinstitut des Freistaats Bayern, DE; 2fortiss GmbH, DE Abstract We propose a methodology for designing dependable Artificial Neural Networks (ANNs) by extending the concepts of understandability, correctness, and validity that are crucial ingredients in existing certification standards. We apply the concept in a concrete case study for designing a highway ANN-based motion predictor to guarantee safety properties such as impossibility for the ego vehicle to suggest moving to the right lane if there exists another vehicle on its right. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:15 | 8.5.6 | IOT SECURITY ASSESSMENT THROUGH THE INTERFACES P-SCAN TEST BENCH PLATFORM Speaker: Thomas Maurin, CEA, Leti, Univ. Grenoble Alpes, FR Authors: Thomas Maurin1, Laurent-Frédéric Ducreux1, George Caraiman2 and Philippe Sissoko2 1CEA Leti, Univ. Grenoble Alpes, FR; 2LCIE Bureau Veritas, FR Abstract The recent, massive and always-growing usage of communicating objects exchanging data over interconnected networks makes these objects vulnerable to cyber-attacks.Ranging from mainstream industrial devices to IoT products, the P-SCAN test platform is designed as a convenient solution to democratize connected objects security assessment. Associated to guidelines easing the definition of a device security target, the platform provides a library of test suites which enables automating the process of testing security features on the device's communication interfaces. As technologies evolve, the platform is designed to be scalable and customisable (new interfaces, new standard test suites, specific test cases with respect to new Common Vulnerabilities and Exposures) to detect potential vulnerabilities. This paper explains the identified business needs and market segment, the related value proposition and gives an overview of the provided technical solution. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |