Date: Wednesday 21 March 2018
Time: 14:30 - 16:00
Location / Room: Konf. 5
Chair:
Petru Eles, Linköping University, SE
Co-Chair:
Akash Kumar, Technische Universität Dresden, DE
Dependability is a crucial aspect of embedded software systems. This session focuses on achieving dependability in different stages of the embedded software life cycle: requirements engineering, design, and maintenance. In particular, the papers presented in this session will address (1) contract based requirement engineering for cyber-physical systems, (2) formal analysis of code using SMT-based symbolic execution to deal with hardware faults, and (3) non-intrusive runtime trace analysis using FPGAs.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.7.1 | CHASE: CONTRACT-BASED REQUIREMENT ENGINEERING FOR CYBER-PHYSICAL SYSTEM DESIGN Speaker: Pierluigi Nuzzo, University of Southern California, US Authors: Pierluigi Nuzzo1, Michele Lora2, Yishai Feldman3 and Alberto Sangiovanni-Vincentelli4 1University of Southern California, US; 2University of Verona, IT; 3IBM Research, Haifa, IL; 4University of California at Berkeley, US Abstract This paper presents CHASE, a framework for requirement capture, formalization, and validation for cyber-physical systems. CHASE combines a practical front-end formal specification language based on patterns with a rigorous verification back-end based on assume-guarantee contracts. The front-end language can express temporal properties of networks using a declarative style, and supports automatic translation from natural-language constructs to low-level mathematical languages. The verification back-end leverages the mathematical formalism of contracts to reason about system requirements and determine inconsistencies and dependencies between them. CHASE features a modular and extensible software infrastructure that can support different domain-specific languages, modeling formalisms, and analysis tools. We illustrate its effectiveness on industrial design examples, including control of aircraft power distribution networks and arbitration of a mixed-criticality automotive bus. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 7.7.2 | RESILIENCE EVALUATION VIA SYMBOLIC FAULT INJECTION ON INTERMEDIATE CODE Speaker: Hoang M. Le, University of Bremen, DE Authors: Hoang M. Le1, Vladimir Herdt1, Daniel Grosse2 and Rolf Drechsler2 1University of Bremen, DE; 2University of Bremen/DFKI GmbH, DE Abstract There is a growing need for error-resilient software that can tolerate hardware faults as well as for new resilience evaluation techniques. For the latter, a promising direction is to apply formal techniques in fault injection-based evaluations to improve the coverage of evaluation results. Building on the recent development of Software-implemented Fault Injection (SWiFI) techniques on compiler's intermediate code, this paper proposes a novel resilience evaluation framework combining LLVM-based SWiFI and SMT-based symbolic execution. This novel combination offers significant advantages over state-of-the-art approaches with respect to accuracy and coverage. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 7.7.3 | ONLINE ANALYSIS OF DEBUG TRACE DATA FOR EMBEDDED SYSTEMS Speaker: Philip Gottschling, TU Darmstadt, DE Authors: Normann Decker1, Boris Dreyer2, Philip Gottschling2, Christian Hochberger2, Alexander Lange3, Martin Leucker1, Torben Scheffel1, Simon Wegener4 and Alexander Weiss3 1Universität zu Lübeck, DE; 2TU Darmstadt, DE; 3Accemic Technologies GmbH, DE; 4AbsInt Angewandte Informatik GmbH, DE Abstract Modern multi-core Systems-on-Chip (SoC) provide very high computational power. On the downside, they are hard to debug and it is often very difficult to understand what is going on in these chips because of the limited observability inside the SoC. Chip manufacturers try to compensate this difficulty by providing highly compressed trace data from the individual cores. In the past, the common way to deal with this data was storing it for later offline analysis, which severely limits the time span that can be observed. In this contribution, we present an FPGA-based solution that is able to process the trace data in real-time, enabling continuous observation of the state of a core. Moreover, we discuss applications enabled by this technology. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018
Wednesday, March 21, 2018
Thursday, March 22, 2018
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