Date: Wednesday 21 March 2018
Time: 11:00 - 12:30
Location / Room: Saal 2
Chair:
Aitken Rob, ARM, US
This session presents energy-efficient digital design approaches using new transistor ideas and their experimental demonstrations. Examples include negative capacitance-based gate control, carbon nanotube-based channels, and polarity-control by design.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.1.1 | NEGATIVE CAPACITANCE TRANSISTORS Author: Michael Hoffmann, NaMLab gGmbH, DE Abstract A transistor looking from the gate essentially acts as a series combination of two capacitors: the gate oxide capacitor and the channel capacitor. When the gate oxide is an appropriate ferroelectric, this series combination can stabilize the ferroelectric material at a state of negative capacitance. At this state, the total capacitance of the series combination is enhanced, leading to more charge at the channel at the same voltage. This boost of charge, in turn, leads to larger current at the same voltage. In fact, this boost makes it possible to reduce supply voltage of transistors below the traditional Boltzmann limit --- often termed as the Boltzmann tyranny. In the recent years, many groups around the world, both in academy and in the industry, have demonstrated the fundamental effect and the Negative Capacitance Transistors. In this work, we shall describe the physical origin of the negative capacitance effect and our current understanding of the recent experimental work. We shall also discuss potential ways to optimize devices that could lead to significant improvement in energy efficiency for next generation computers. |
| 11:30 | 6.1.2 | CARBON NANOTUBE FILM-BASED CMOS AND OPTOELECTRONIC DEVICES AND INTEGRATED SYSTEMS Author: Lian-Mao Peng, Peking University, CN Abstract Carbon nanotube (CNT)-based electronics has been considered one of the most promising candidates to replace Si complementary metal-oxide-semiconductor (CMOS) technology, which will soon meet its performance limit. Prototype device studies on individual CNTs revealed that CNT based devices have the potential to outperform Si CMOS technology in both performance and power consumption, especially at sub-10 nm technology nodes, which are close to the theoretical limits; and various optoelectronic device such as light-emitting diodes, photodetectors and photovoltaic (PV) cells have been demonstrated. In this talk, I will discuss the use of randomly oriented CNT film to build CNT CMOS and optoelectronic devices, and show that the performance of CNT film devices and systems can be dramatically improved by optimizing the material purity, device structure and fabrication processes, thus yielding CNT devices with outstanding performance comparable to that of Si CMOS and ICs working in the GHz regime, and integrated electronic and optoelectronic systems for communications between nanoelectronic circuits using CNT devices. |
| 12:00 | 6.1.3 | TOWARDS HIGH-PERFORMANCE POLARITY-CONTROLLABLE FETS WITH 2D MATERIALS Speaker: Pierre-Emmanuel Gaillardon, University of Utah, US Authors: Giovanni V. Resta1, Jorge Romero Gonzalez2, Yashwanth Balaji3, Tarun Kumar Agarwal3, Dennis Lin3, Francky Catthoor3, Iuliana P. Radu3, Giovanni De Micheli1 and Pierre-Emmanuel Gaillardon4 1Integrated System Laboratory – EPFL, CH; 2Laboratory of NanoIntegrated Systems (LNIS), Department of Electrical and Computer Engineering, University of Utah, US; 3IMEC, BE; 4University of Utah, US Abstract As scaling of conventional silicon-based electronics is reaching its ultimate limit, two-dimensional semiconducting materials of the transition-metal-dichalcogenides family, such as MoS2 and WSe2, are considered as viable candidates for next-generation electronic devices. Fully relying on electrostatic doping, polarity-controllable devices, that use additional gate terminals to modulate the Schottky barriers at source and drain, can strongly take advantages of 2D materials to achieve high on/off ratio and low leakage floor. Here, we provide an overview of the latest advances in 2D material processes and growth. Then, we report on the experimental demonstration of polarity-controllable devices fabricated on 2D-WSe2 and study the scaling trends of such devices using ballistic self-consistent quantum simulations. Finally, we discuss the circuit-level opportunities of such technology. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session Lunch Break in Großer Saal and Saal 1
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018
Wednesday, March 21, 2018
Thursday, March 22, 2018
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