Date: Wednesday 29 March 2017
Time: 08:30 - 10:00
Location / Room: 3A
Chair:
Daniel Grosse, University of Bremen, DE
Co-Chair:
Alper Sen, Bogazici University, TR
The section introduces system-level frameworks for addressing memory tracing, timing estimation, real-time verification, and reliability degradation.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.4.1 | (Best Paper Award Candidate) PERFORMANCE IMPACTS AND LIMITATIONS OF HARDWARE MEMORY-ACCESS TRACE-COLLECTION Speaker: Graham Holland, Simon Fraser University, CA Authors: Nicholas C. Doyle1, Eric Matthews1, Graham Holland1, Alexandra Fedorova2 and Lesley Shannon1 1Simon Fraser University, CA; 2University of British Columbia, CA Abstract In today's multicore architectures, complex interactions between applications in the memory system can have a significant, and highly variable, impact on application execution time. System designers typically use hardware counters to profile execution behaviours and diagnose performance problems. However, hardware counters are not always sufficient and some problems are best identified with full memory access traces. Collecting these traces in software is very expensive. Our work explores using dedicated hardware for memory-access trace collection. We focus on analyzing the limitations of hardware data collection and its impacts on application performance. The key feature of our study is that it is performed on actual hardware using two very different CPU platforms: 1) the PolyBlaze multicore soft processor and 2) the ARM Cortex-A9. In both cases, the data collection is implemented on an FPGA. Using micro-benchmarks designed to test the bounds of memory access behaviour, we illustrate the operational regions of data collection and the impact on system performance. By examining the bandwidth bottlenecks that limit the rate of data collection, as well as hardware architecture choices that can aggravate the impact on application performance, we provide guidelines that can be used to extrapolate our analysis to other systems and processor architectures. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 5.4.2 | CONTEXT-SENSITIVE TIMING AUTOMATA FOR FAST SOURCE LEVEL SIMULATION Speaker: Sebastian Ottlik, FZI Research Center for Information Technology, DE Authors: Sebastian Ottlik1, Christoph Gerum2, Alexander Viehl3, Wolfgang Rosenstiel4 and Oliver Bringmann4 1FZI Research Center for Information Technology, DE; 2University of Tuebingen, DE; 3FZI Forschungszentrum Informatik, DE; 4University of Tuebingen / FZI, DE Abstract We present a novel technique for efficient source level timing simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level timing simulation. However, a direct application of the binary level approach to source level simulation reduces simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based simulation technique. The proposed context-sensitive timing automata enable an efficient evaluation of complex simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache simulation. The accelerated simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 5.4.3 | MARS: A FLEXIBLE REAL-TIME STREAMING PLATFORM FOR TESTING AUTOMATION SYSTEMS Speaker: Alexandru Moga, ABB Research, CH Authors: Raphael Eidenbenz, Alexandru Moga, Thanikesavan Sivanthi and Carsten Franke, ABB Corporate Research, CH Abstract Trends in industrial automation systems are placing more importance on using streams of digitized data to perform various automation functions in real-time, e.g., power, process, and factory automation. To ensure high reliability and availability, individual devices or (sub-)systems thereof need to be tested with respect to their expected real-time behavior in the system context at various stages during product and project life cycle. In this paper, we introduce a real-time streaming platform called MARS that provides the means to monitor (M) high frequency data streams, analyze (A) them with respect to their properties, record data traffic (R) based on user-specified rules, and simulate data traffic (S) and in general the behavior of certain functions of one or more devices according to highly customizable scenarios. We present the design principles of MARS, the real-time software architecture, and evaluation results. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:45 | 5.4.4 | SERD: A SIMULATION FRAMEWORK FOR ESTIMATION OF SYSTEM LEVEL RELIABILITY DEGRADATION Speaker: Saurav Ghosh, IIT Kharagpur, IN Authors: Saurav Kumar Ghosh1 and Dey Soumyajit2 1Dept. of CSE, IIT Kharagpur, IN; 2IIT Kharagpur, IN Abstract Development of highly reliable embedded controlsystems is typically performed following the model driven engineering paradigm. Such systems involve software controlled interaction of mechanical subsystems. The aging of the overall system depends on the physical aging or reliability decay of the underlying mechanical components. The reliability of such components degrade according to their rate of usage which again is governed by the software control logic and input environment. Such dependencies of component reliabilities make the problem of deriving system level reliability degradation using exact methods combinatorially intractable. Given the fact that model driven system design advocates the usage of initial high level system models, methods for early stage lifetime reliability and reliability degradation estimation based on such initial models should definitely aid in robust high assurance engineering of such software controlled physical systems. The present work proposes SERD, a lightweight, scalable simulation framework for embedded control systems. It can accommodate active as well as quiescent reliability decay rates of underlying mechanical components. It uses path based reliability modeling to estimate the reliability degradation of component based systems that are controlled by software logic. Its efficacy is further demonstrated using a thorough case study. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP2-15, 89 | A NOVEL WAY TO EFFICIENTLY SIMULATE COMPLEX FULL SYSTEMS INCORPORATING HARDWARE ACCELERATORS Speaker: Nikolaos Tampouratzis, Technical University of Crete, GR Authors: Nikolaos Tampouratzis1, Konstantinos Georgopoulos2 and Ioannis Papaefstathiou3 1Technical University of Crete, GR; 2Telecommunication Systems Institute, Technical University of Crete, GR; 3Technical university of Crete, GR Abstract The breakdown of Dennard scaling coupled with the persistently growing transistor counts severally increased the importance of application-specific hardware acceleration; such an approach offers significant performance and energy benefits compared to general-purpose solutions. In order to thoroughly evaluate such architectures, the designer should perform a quite extensive design space exploration so as to evaluate the tradeoffs across the entire system. The design, until recently, has been predominantly done using Register Transfer Level (RTL) languages such as Verilog and VHDL, which, however, lead to a prohibitively long and costly design effort. In order to reduce the design time a wide range of both commercial and academic High-Level Synthesis (HLS) tools have emerged; most of those tools, handle hardware accelerators that are described in synthesisable SystemC. The problem today, however, is that most simulators used for evaluating the complete user applications (i.e. full-system CPU/Mem/Peripheral simulators) lack any type of SystemC accelerator support. Within this context this paper presents a novel simulation environment comprised of a generic SystemC accelerator and probably the most widely known fullsystem simulator (i.e. GEM5). The proposed system is the only solution supporting the very important feature of global synchronization across the integrated simulation; furthermore it has been evaluated based on two different computationallyintensive use cases and the final results demonstrate that the presented approach is orders of magnitude faster than the existing ones. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:01 | IP2-16, 222 | AUTOMATIC ABSTRACTION OF MULTI-DISCIPLINE ANALOG MODELS FOR EFFICIENT FUNCTIONAL SIMULATION Speaker: Franco Fummi, Università degli Studi di Verona, IT Authors: Enrico Fraccaroli1, Michele Lora1 and Franco Fummi2 1University of Verona, IT; 2Universita' di Verona, IT Abstract Multi-discipline components introduce problems when inserted within virtual platforms of Smart Systems for functional validation. This paper lists the most common emerging problems and it proposes a set of solutions to them. It presents a set of techniques, unified in an automatic abstraction methodology, useful to achieve fast analog mixed-signal simulation even when different physical disciplines and modeling styles are combined into a single analog model. The paper makes use of a complex case study.It deals with multiple-discipline descriptions, non-electrical conservative models, non-linear equation systems, and mixed time/frequency domain models. The original component behavior has been modeled in Verilog-AMS by using electrical, mechanical and kinematic equations. Then, it has been abstracted and integrated within a virtual platform of a mixed-signal smart system for efficient functional simulation. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:02 | IP2-19, 23 | AUTOMATIC CONSTRUCTION OF MODELS FOR ANALYTIC SYSTEM-LEVEL DESIGN SPACE EXPLORATION PROBLEMS Speaker: Seyed-Hosein Attarzadeh-Niaki, Shahid Beheshti University (SBU), IR Authors: Seyed-Hosein Attarzadeh-Niaki1 and Ingo Sander2 1Shahid Beheshti University (SBU), IR; 2KTH Royal Institute of Technology, SE Abstract Due to the variety of application models and also the target platforms used in embedded electronic system design, it is challenging to formulate a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework for automatic construction of system-level DSE problem models based on a coherent, constraint-based representation of system functionality, flexible target platforms, and binding policies. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from different combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. Another potential advantage of this approach is that constructed models can be solved using a variety of standard and ad-hoc solvers and search heuristics. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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